1. Field of the Invention
The present invention relates to a method of fabricating semiconductor memory devices, and more particularly, to a method of fabricating a capacitor of a semiconductor memory device.
2. Description of the Related Art
With an increase in the integration of dynamic random access memories (hereinafter abbreviated as DRAM), methods have been proposed, of thinning a dielectric film of a capacitor to increase capacitance in a restricted cell area, or of changing the structure of a capacitor lower electrode to a three-dimensional structure to increase the effective area of a capacitor.
However, even though the above-proposed methods are adopted, it is difficult to obtain a capacitance necessary for device operation in a memory device of 1 G DRAM or more from an existing dielectric. In order to solve the above problem, research has been actively conducted into substituting the dielectric film of a capacitor with a thin film formed of a material having high permittivity, such as,
Ta.sub.2 O.sub.5, (Ba,Sr)TiO.sub.3 (BST), PbZrTiO.sub.3 (PZT), (Pb,La)(Zr,Ti)O.sub.3 (PLZT), among others.
In the capacitor using the above-described high dielectric film, metals of the platinum group or oxides thereof, e.g., Pt, Ir, Ru, RuO.sub.2, IrO.sub.2, etc., instead of polysilicon are used as an electrode material.
Meanwhile, in a stacked-type capacitor having a three-dimensional structure, the lower electrode becomes higher and the interval between electrodes becomes narrower as the DRAM becomes more highly integrated. Due to limits in the platinum film etch technology, difficulties in separating storage nodes have appeared.
In order to solve this particular problem, a capacitor fabrication method by which difficulties in etching a platinum film can be avoided while using the above high dielectric film has been developed in many fields. For example, a concave capacitor has been proposed by Y. Kohyama et al., Symposium on VLSI Technology Digest of Technical Papers, p. 17, 1997.
According to a method of fabricating the proposed concave capacitor, an interlayer dielectric film is formed on a semiconductor substrate, a storage node hole is formed in the interlayer dielectric film, and ruthenium (Ru) is deposited to a predetermined thickness in the storage node hole, thereby forming a storage electrode.
When the concave capacitor is formed as described above, difficulties in the platinum-group metal etch process can be avoided, and the height of the storage node can be arbitrarily controlled as well. However, when forming the storage node of the concave capacitor, the sidewall of the interlayer dielectric film exposed by the storage node hole is weakly coupled to the storage node, which causes a phenomenon in which the storage node is lifted from the interlayer dielectric film upon subsequent deposition or thermal treatment. When this lifting phenomenon occurs, stress is applied to the entire structure of the capacitor. Thus, a bad influence can be exerted on the dielectric film of the capacitor and a plate electrode. In addition, electrical characteristics may be degraded, due to leakage current in a completely-fabricated capacitor.